Various Complementary Metal-Oxide Semiconductor (CMOS) driver architectures exist for high-speed digital transmission. The CMOS driver architectures encounter problems of low output voltage swing when the supply voltage approaches 1.2V. This problem arises because transistors in the signal path consume voltage headroom, which reduces the amplitude of the differential output voltage.
If the driver has an n-channel Metal-Oxide Semiconductor (NMOS) digital-to-analog converter (DAC) (NDAC), the common mode output level is controlled by a common mode feedback (CMFB) circuit and a p-channel Metal-Oxide Semiconductor (PMOS). Using a fixed PMOS, the ratio of the PMOS resistance to the NDAC resistance is not constant. The variation in voltage across the PMOS is large and not optimized, which reduces overall available output voltage.